Parallel Sparse LU Factorization of Power Flow Jacobian using GPU

Gnanavignesh, R and Shenoy, UJ (2019) Parallel Sparse LU Factorization of Power Flow Jacobian using GPU. In: 2019 IEEE Region 10 Conference: Technology, Knowledge, and Society, TENCON 2019, 17-20 October 2019, Hotel Grand Hyatt Kerala; India, pp. 1857-1862.

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Abstract

Parallelizing the LU factorization of sparse Jacobian matrices reduces the execution time of the power flow algorithm which aids in real time control of the power system. In this paper, acceleration of LU factorization by employing different Graphical Processing Units(GPUs) is discussed. The hybrid column based right-looking LU factorization algorithm is found to be more amenable for GPU implementation. The structural symmetry property of non-zeros in the matrix is exploited to maximize the column/node level parallelization through a matrix re-ordering scheme obtained from Jess-Kees' algorithm. Also the influence of different fill-in reducing matrix re-orderings in the context of parallelization and execution time is discussed. The proposed method is tested on a set of power flow Jacobians with dimensions ranging from 4438 to 1136128 on different GPUs. Results from the current work demonstrate scalability of the proposed method with progressively powerful GPUs yielding better execution times. Efficacy of the proposed method is corroborated by improved speedup in execution when compared with CPU-based serial sparse system solvers like UMFPACK and KLU.

Item Type:	Conference Paper
Publication:	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	Copyright of this article belongs to IEEE
Keywords:	Factorization; Graphics processing unit; Jacobian matrices; Program processors; Real time control, Elimination tree; Graphical processing unit (GPUs); Jess-Kees' method; LU factorization; Power flow algorithm; Power flow Jacobian; Power flows; Structural symmetry, Electric load flow
Department/Centre:	Division of Electrical Sciences > Electrical Engineering
Date Deposited:	24 Feb 2020 11:35
Last Modified:	24 Feb 2020 11:35
URI:	http://eprints.iisc.ac.in/id/eprint/64441

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