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Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems

Gupta, Sarthak and Kumar, Pratik and Paul, Tathagata and van Schaik, Andre and Ghosh, Arindam and Thakur, Chetan Singh (2019) Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems. In: SCIENTIFIC REPORTS, 9 .


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Official URL: https://www.doi.org/10.1038/s41598-019-51606-x


Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Nature Publishing Group
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Division of Physical & Mathematical Sciences > Physics
Date Deposited: 19 Dec 2019 09:40
Last Modified: 19 Dec 2019 09:40
URI: http://eprints.iisc.ac.in/id/eprint/63959

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