Timed Petri Net Models of Multithreaded Multiprocessor Architectures

Govindarajan, R and Suciu, F and Zuberek, WM (1997) Timed Petri Net Models of Multithreaded Multiprocessor Architectures. In: Seventh International Workshop on Petri Nets and Performance Models, 1997, 3-6 June, Saint Malo, 153 -162.

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Abstract

Multithreaded distributed-memory multiprocessor architectures are composed of a number of (multi- threaded) processors, each with its memory, and an interconnection network. The long memory latencies and unpredictable synchronization delays are tolerated by context switching, i.e., by suspending the current thread and switching the processor t o another ‘ready’ thread provided such a thread is available. Because of very simple representation of concurrency and synchronization, timed Petri net models seem to be well suited for modeling and evaluation of such architectures. However, accurate net models of multi-threaded multiprocessors become quite complicated, so their analysis can be a nontrivial task. This paper describes a timed colored Petri net model of a multithreaded multiprocessor architecture, and presents some results obtained by simulation of this model. A simplified approach to modeling such architectures is also proposed.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	25 Aug 2008
Last Modified:	11 Jan 2013 10:55
URI:	http://eprints.iisc.ac.in/id/eprint/6393

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