Yadav, Apurv Kumar and Gopakumar, K and Raj, Krishna R and Umanand, Loganathan and Bhattacharya, Subhashish and Jarzyna, Wojciech (2019) A Hybrid 7-Level Inverter Using Low-Voltage Devices and Operation With Single DC-Link. In: IEEE TRANSACTIONS ON POWER ELECTRONICS, 34 (10). pp. 9844-9853.
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Abstract
This paper proposes a new 7-level inverter topology for induction motor drives. It is a hybrid topology formed by cascading a 5-level active neutral-point-clamped inverter with a 3-level T-type converter. It is obtained using low-voltage semiconductor devices with voltage blocking capability of Vdc/3 and Vdc/6. The topology uses three floating capacitors per phase, which are balanced within a pulsewidth modulation (PWM) switching duration using switching-state redundancies for each pole-voltage level. Topology forms two stacks at the front-end, which requires individual symmetrical de source. The analysis of switching loss and conduction loss is performed and compared with some of the existing 7-level multi-level inverters reported in various literatures to show the advantages of the proposed topology. Furthermore, the single dc source operation with two stacked capacitors and closed-loop control of neutral-point voltage using symmetrical six-phase induction motor is proposed. The voltage-control algorithms fin. floating capacitors and dc-link stacked capacitors are proposed, which are independent of load power factor and modulation index. Open-loop V/f and closed-loop rotor field oriented control are performed, and various results at steady and transient states are presented to validate the aforementioned claims.
Item Type: | Journal Article |
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Publication: | IEEE TRANSACTIONS ON POWER ELECTRONICS |
Publisher: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Additional Information: | copyright for this article belongs to IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Keywords: | 7-level inverter; hybrid multi-level inverter (MLI); induction motor (IM) drive; multi-level converter; neutral-point voltage (NPV) |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 21 Aug 2019 09:51 |
Last Modified: | 21 Aug 2019 09:51 |
URI: | http://eprints.iisc.ac.in/id/eprint/63282 |
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