Sinha, Rajat and Bhattacharya, Prasenjit and Sambandan, Sanjiv and Shrivastava, Mayank (2018) On the ESD Behavior of a-Si:H based Thin Film Transistors: Physical Insights, Design and Technological Implications. In: IEEE International Reliability Physics Symposium Proceedings, 11-15 March 2018, Burlingame, CA, USA.
![]() |
PDF
Iee_int_rel_phy_sym_pro_3e.21_2018 - Published Version Restricted to Registered users only Download (1MB) | Request a copy |
Abstract
In this work, we present detailed physical and technological insights into the ESD behavior of a-Si:H TFTs. Pre-Breakdown mechanism is investigated using Electron microscopy, Raman spectroscopy and on-the-fly I-V/ C-V measurements in between TLP stress. Competing mechanisms of device failure and effect of various performance parameters on failure threshold are investigated. Effect of channel dimensions on failure mechanism is thoroughly explored. For the first time, ESD behavior of a-Si:H display technology based Gated diodes and Resistors is reported. Detailed investigation on Drain Underlap devices and their possible usage as I/O protection device in a-Si:H technology is discussed.
Item Type: | Conference Proceedings |
---|---|
Series.: | International Reliability Physics Symposium |
Publisher: | IEEE |
Additional Information: | Copyright for this article belongs to IEEE |
Keywords: | Amorphous silicon; Electrostatic Discharge; Thin film transistors; Degradation; Dielectric breakdown; Gated Diodes; Drain Underlap |
Department/Centre: | Division of Electrical Sciences > Electrical Communication Engineering > Electrical Communication Engineering - Technical Reports |
Date Deposited: | 20 Jun 2019 18:36 |
Last Modified: | 09 Jul 2019 07:08 |
URI: | http://eprints.iisc.ac.in/id/eprint/63008 |
Actions (login required)
![]() |
View Item |