Contact and Junction Engineering in Bulk FinFET Technology for Improved ESD/Latch-up Performance with Design Trade-offs and its Implications on Hot Carrier Reliability

Paul, Milova and Kumar, BSampath and Gossner, Harald and Shrivastava, Mayank (2018) Contact and Junction Engineering in Bulk FinFET Technology for Improved ESD/Latch-up Performance with Design Trade-offs and its Implications on Hot Carrier Reliability. In: 2018 IEEE International Reliability Physics Symposium, IRPS 2018; Burlingame; United States; 11 March, 11-15 March 2018, Burlingame, CA, USA.

PDF con-jun-eng-2018.pdf - Published Version Restricted to Registered users only Download (564kB) | Request a copy

Abstract

In this work, the role of contact and junction engineering to improve ESD, Latch-up robustness as well as hot carrier reliability is discussed using 3D TCAD simulations. A FinFET technology calibrated to published data of a 14 nm technology is investigated. S/D contact and junction engineering in FinFETs can boost the ESD robustness by a factor of 6x compared to the basic process, however, adversely affects the hot carrier reliability. The trade-off of the essential technology guidelines for maximizing the overall reliability behavior and ESD/LU robustness are derived. Based on these guidelines, a hybrid contact/junction technology is proposed.

Item Type:	Conference Proceedings
Series.:	International Reliability Physics Symposium
Publisher:	IEEE
Additional Information:	IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, MAR 11-15, 2018
Keywords:	Bulk FinFET; Electrostatic Discharge; Hot Carrier Induced (HCI) Degradation
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering Division of Electrical Sciences > Electrical Communication Engineering > Electrical Communication Engineering - Technical Reports
Date Deposited:	20 Jun 2019 18:29
Last Modified:	21 Jun 2019 08:58
URI:	http://eprints.iisc.ac.in/id/eprint/63005

Actions (login required)

View Item