Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications

Kumar, B Sampath and Paul, Milova and Shrivastava, Mayank and Gossner, Harald (2018) Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications. In: 30th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), MAY 13-17, 2018, Chicago, IL, pp. 72-75.

PDF ISPSD_2018.pdf - Published Version Restricted to Registered users only Download (1MB) | Request a copy

Abstract

In this paper1, Drain extended FinFET device design and the challenges associated with the performance and reliability are discussed. Physical insights into the performance vs. reliability trade-off for the Fin enabled high voltage designs is elaborated and compared with their planar counterpart (DeMOS). Effect of Fin width discretization over ESD reliability, Safe Operating Area and HCI reliability are discussed.

Item Type:	Conference Paper
Series.:	International Symposium on Power Semiconductor Devices & ICs
Publisher:	IEEEMinistry of Human Resource and Development. Government of India
Additional Information:	The copyright of this article belongs to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Drain Extended; ESD; finFET; HCI; reliability; Safe Operating Area
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	24 May 2019 10:05
Last Modified:	26 Jul 2022 11:22
URI:	https://eprints.iisc.ac.in/id/eprint/62759

Actions (login required)

View Item