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A RISC-V ISA Compatible Processor IP for SoC

Budi, Suseela and Gupta, Pradeep and Varghese, Kuruvilla and Bharadwaj, Amrutur (2018) A RISC-V ISA Compatible Processor IP for SoC. In: 2018 INTERNATIONAL SYMPOSIUM ON DEVICES, CIRCUITS AND SYSTEMS (ISDCS), MAR 29-31, 2018, Howrah, INDIA.

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Official URL: https://doi.org/10.1109/ISDCS.2018.8379629


The emergence of System-on-Chip technology has brought in opportunities in the form of reduced cycle time, superior performance and time-to-market considerations. Our work focusses on a new processor for a System on Chip. The system has a 32-bit, 5-stage pipelined processor, memory subsystem with virtual memory support, interrupt controller, memory error control module, and UART. The processor is based on RISC-V ISA. It supports Integer, Multiply, and Atomic instructions. Memory subsystem includes split caches and translation lookaside buffers. Interrupt controller supports four levels of preemptive priority and preemption can be programmed for individual interrupts. Memory error control module provides single error correction and double error detection for main memory. Wishbone B.3 bus standard is adopted as on-chip bus protocol. The design is implemented on Virtex-7 (XC7VX485tffg1761-2) board and achieves a peak clock frequency of 100MHz.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: International Symposium on Devices, Circuits and Systems (ISDCS), Howrah, INDIA, MAR 29-31, 2018
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 28 Jan 2019 10:12
Last Modified: 28 Jan 2019 10:12
URI: http://eprints.iisc.ac.in/id/eprint/61505

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