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A New Two-Phase Five-Level Converter for Three-Phase Isolated Grid-Tied Systems With Inherent Capacitor Balancing and Reduced Component Count

Naik, B Satish and Umanand, L and Gopakumar, K and Reddy, B Subba (2018) A New Two-Phase Five-Level Converter for Three-Phase Isolated Grid-Tied Systems With Inherent Capacitor Balancing and Reduced Component Count. In: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 6 (3). pp. 1325-1335.

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Official URL: http://dx.doi.org/10.1109/JESTPE.2018.2805520

Abstract

This paper presents a single dc source fed five-level converter topology for medium-voltage high-power isolated grid-tied systems with reduced power switch count. The proposed converter generates two-phase systems of voltages that are further converted to three phases by using Scott-T transformer connection. Compared to existing topologies, the proposed converter requires fewer power switches, gate drivers, and power diodes. An added advantage is that only a single dc source is required. An important feature of this topology is that the dc-link capacitor voltages have an inherent ability to self-balance by themselves without the need for extra balance circuitry and special control algorithms. The voltage stress across the power devices of the proposed converter is equal to half of dc-link voltage. A level-shifted carrier-based pulsewidth modulation scheme is used to inject current into the grid at unity power factor. Analysis and simulation and experimental results are presented to validate the performance of the proposed converter under grid-tied operation.

Item Type: Journal Article
Publication: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Additional Information: Copy right for this article belong to IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 04 Sep 2018 15:43
Last Modified: 12 Nov 2018 15:44
URI: http://eprints.iisc.ac.in/id/eprint/60572

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