Ahlawat, Satyadev and Vaghani, Darshit and Tudu, Jaynarayan and Suhag, Ashok (2017) A Cost Effective Technique for Diagnosis of Scan Chain Faults. In: 21st International Symposium on VLSI Design and Test (VDAT), JUN 29-JUL 02, 2017, Indian Inst Technol Roorkee, Roorkee, INDIA, pp. 191-204.
Full text not available from this repository. (Request a copy)Abstract
Scan based diagnosis plays a critical role in failure mode analysis for yield improvement. However, as the logic circuitry associated with scan chains constitute a significant fraction of a chip's total area the scan chain itself can be subject to defects. In some cases, it has been observed that scan chain failures may account up to 50% of total chip failures. Hence, scan chain testing and diagnosis have become very crucial in recent years. This paper proposes a hardware-assisted low complexity and area efficient scan chain diagnosis technique. The proposed technique is simple to implement and provides maximum diagnostic resolution for stuck-at faults. The proposed technique can be further extended to diagnose scan chain's timing faults.
| Item Type: | Conference Proceedings |
|---|---|
| Series.: | Communications in Computer and Information Science |
| Publisher: | SPRINGER-VERLAG BERLIN, HEIDELBERGER PLATZ 3, D-14197 BERLIN, GERMANY |
| Additional Information: | Copyright of this article belong to SPRINGER-VERLAG BERLIN, HEIDELBERGER PLATZ 3, D-14197 BERLIN, GERMANY |
| Department/Centre: | Division of Electrical Sciences > Computer Science & Automation |
| Date Deposited: | 20 Jul 2018 16:36 |
| Last Modified: | 20 Jul 2018 16:36 |
| URI: | http://eprints.iisc.ac.in/id/eprint/60264 |
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