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A 13.5 bit 1.6 mW 3rd order CT Sigma Delta ADC for Integrated Capacitance Sensor Interface

Gaggatur, Javed S and Banerjee, Gaurab (2017) A 13.5 bit 1.6 mW 3rd order CT Sigma Delta ADC for Integrated Capacitance Sensor Interface. In: 30th IEEE International System-on-Chip Conference (SOCC), SEP 05-08, 2017, Munich, GERMANY, pp. 40-44.

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Official URL: http://dx.doi.org/10.1109/SOCC.2017.8226003


An integrated capacitance sensor interface is proposed with three programmable gain stages to measure femtofarad capacitance. The capacitance sensor interface is a differential measurement set-up to measure the change in capacitance over a fixed nominal capacitance. The programmable gain stages are used to change the gain settings to operate for a wide range capacitance measurement. The implemented continuous time Sigma Delta ADC is a third-order cascade of integrators feedforward topology with a signal bandwidth of 10 kHz. The ADC has a measured peak dynamic range of 84.5 dB while consuming 1.6 mW. The measured figure of merit (FoM) is 3.107 pJ-mm(2)/conversion at a clock frequency of 6.4 MHz having an active area of 0.45 mm(2). The ADC was applied in the femtofarad capacitance measurement using a 0.3 pF - 1.2 pF variable capacitor typically encountered in MEMS-based sensor applications like pressure/humidity/flow sensing in System-in-Package (SiP) or Systems-on-Chip (SoC).

Item Type: Conference Proceedings
Additional Information: 30th IEEE International System-on-Chip Conference (SOCC), Munich, GERMANY, SEP 05-08, 2017
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 13 Apr 2018 19:57
Last Modified: 13 Apr 2018 19:57
URI: http://eprints.iisc.ac.in/id/eprint/59548

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