Work-in-Progress: REDEFINE (R)(TM) - A Case for WCET-friendly Hardware Accelerators for Real time Applications

Madhu, Kavitha and Singla, Tarun and Nandy, S K and Narayan, Ranjani and Neumann, Francois and Baufreton, Philippe (2017) Work-in-Progress: REDEFINE (R)(TM) - A Case for WCET-friendly Hardware Accelerators for Real time Applications. In: International Conference on Compilers Architectures and Synthesis For Embedded Systems (CASES), OCT 15-20, 2017, Seoul, SOUTH KOREA.

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Abstract

REDEFINE is a distributed dynamic dataflow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). This paper dwells on the flexibility of REDE-FINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.

Item Type:	Conference Proceedings
Series.:	International Conference on Compilers Architecture and Synthesis for Embedded Systems
Publisher:	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Additional Information:	Copy right for the article belong to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	28 Mar 2018 16:18
Last Modified:	28 Mar 2018 16:18
URI:	http://eprints.iisc.ac.in/id/eprint/59411

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