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Germanane MOSFET for Subdeca Nanometer High-Performance Technology Nodes

Brahma, Madhuchhanda and Bescond, Marc and Logoteta, Demetrio and Ghosh, Ram Krishna and Mahapatra, Santanu (2018) Germanane MOSFET for Subdeca Nanometer High-Performance Technology Nodes. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 65 (3). pp. 1198-1204.

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Official URL: http://dx.doi.org/10.1109/TED.2017.2788463


Ballistic transport in monolayer Germanane MOSFETs is investigated for high-performance (HP) applications. Characteristics of both n- and p-type transistors having channel lengths of 7, 5, and 3 nm are studied and compared against the International Technology Roadmap for Semiconductor (ITRS) target of 2028. Our simulation approach is based on a self-consistent quantum ballistic transportmodel within the framework of the nonequilibrium Green's function formalism and relies on a single-band and a two-band k.p Hamiltonian for n- and p-type channels, respectively. We found that, even for a gate length scaled down to 3 nm, the ON current (I-ON) in n- and p-MOSFETs for a fixed OFF current I-OFF = 100 nA/mu m is as high as similar to 890 and 700 mu A/mu m, respectively. For longer channel lengths, the p-MOSFET can outperform the n-MOSFET in terms of I-ON requirements, as the direct source-to-drain tunneling gets suppressed. Other performance metrics, including gate capacitance, intrinsic switching delay, and switching energy, have also been calculated and found to be comparable to the ITRS 2028 HP technology requirements.

Item Type: Journal Article
Additional Information: Copy right for the article belong to IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited: 19 Mar 2018 18:29
Last Modified: 19 Mar 2018 18:29
URI: http://eprints.iisc.ac.in/id/eprint/59230

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