Five-level inverter scheme for an induction motor drive with simultaneous elimination of commonmode voltage and DC-link capacitor voltage imbalance

Tekwani, PN and Kanchan, RS and Gopakumar, K (2005) Five-level inverter scheme for an induction motor drive with simultaneous elimination of commonmode voltage and DC-link capacitor voltage imbalance. In: IEE Proceedings Electric Power Applications, 152 (6). pp. 1539-1555.

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Abstract

The simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance is achieved in a five-level inverter scheme for an induction motor drive throughout its operating range. A dual five-level inverter-fed open-end-winding induction motor structure is used for the proposed drive. Initially, the operating limitations of achieving this dual task for the five-level inverter configuration are investigated for a single DC power supply. Subsequently, a switching strategy for a five-level inverter topology with two DC power supplies is proposed to achieve the dual task over the entire speed range of the drive. The proposed drive offers a simple power-bus structure with more redundant switching combinations for inverter voltage vectors, and requires a lower voltage-blocking capacity of the power devices as compared with the conventional single five-level inverter-fed drive. As only the availability of redundant switching combinations for inverter voltage vectors is exploited, the dual task is achieved without disturbing the fundamental component of the inverter output voltage and the scheme does not need any extra control circuit hardware. Experimental verification of the proposed scheme is done on a 1.5 kW induction motor drive in the linear as well as overmodulation range.

Item Type:	Journal Article
Publication:	IEE Proceedings Electric Power Applications
Publisher:	IEE
Additional Information:	Copyright of this article belongs to Institution of Electrical Engineers (IEE)
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	16 Mar 2006
Last Modified:	19 Sep 2010 04:24
URI:	http://eprints.iisc.ac.in/id/eprint/5893

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