Dabhade, Swapnil Deelip and Rathna, GN and Chaudhury, Kunal N (2018) A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 65 (2). pp. 1459-1469.
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Abstract
Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, field-programmable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales asO(omega(2)) with the filter width.. In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just O(1) operations for any arbitrary omega. The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.
Item Type: | Journal Article |
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Publication: | IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS |
Publisher: | 10.1109/TIE.2017.2726960 |
Additional Information: | Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA |
Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
Date Deposited: | 12 Jan 2018 09:33 |
Last Modified: | 01 Mar 2019 07:05 |
URI: | http://eprints.iisc.ac.in/id/eprint/58647 |
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