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A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors

Govindarajan, R and Altman, Erik R and Gao, Guang R (2000) A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. In: IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2000, 10-12 July, Boston,Massachusetts, 329 -338.


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Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded processors. Existing techniques deal with either scheduling hardware pipelines to obtain higher throughput or software pipeline-an instruction scheduling technique for iterative computation-loops for exploiting greater ILP. We integrate these techniques to co-schedule hardware and software pipelines to achieve greater instruction throughput. In this paper, we develop the underlying theory of co-scheduling, called the Modulo-Scheduled Pipeline (or MS-Pipeline) theory. More specifically, we establish the necessary and sufficient condition for achieving the maximum throughput in a given pipeline operating under module scheduling. Further, we establish a sufficient condition to achieve a specified throughput, based on which we also develop a methodology for designing the hardware pipelines that achieve such a throughput.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 27 Feb 2006
Last Modified: 19 Sep 2010 04:24
URI: http://eprints.iisc.ac.in/id/eprint/5723

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