A Technique for Low Power, Stuck-at Fault Diagnosable and Reconfigurable Scan Architecture

Kumar, Binod and Nehru, Boda and Pandey, Brajesh and Singh, Virendra and Tudu, Jaynarayan (2017) A Technique for Low Power, Stuck-at Fault Diagnosable and Reconfigurable Scan Architecture. In: IEEE East-West Design and Test Symposium (EWDTS), OCT 14-17, 2016, Yerevan, ARMENIA.

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Abstract

Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.

Item Type:	Conference Proceedings
Publisher:	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Additional Information:	IEEE East-West Design and Test Symposium (EWDTS), Yerevan, ARMENIA, OCT 14-17, 2016
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	10 Jun 2017 04:42
Last Modified:	10 Jun 2017 04:42
URI:	http://eprints.iisc.ac.in/id/eprint/57218

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