Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations

Bondhugula, Uday and Bandishti, Vinayaka and Pananilath, Irshad (2017) Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 28 (5). pp. 1285-1298.

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Abstract

Most stencil computations allow tile-wise concurrent start, i.e., there always exists a face of the iteration space and a set of tiling directions such that all tiles along that face can be started concurrently. This provides load balance and maximizes parallelism. However, existing automatic tiling frameworks often choose hyperplanes that lead to pipelined start-up and load imbalance. We address this issue with a new tiling technique, called diamond tiling, that ensures concurrent start-up as well as perfect load-balance whenever possible. We first provide necessary and sufficient conditions for a set of tiling hyperplanes to allow concurrent start for programs with affine data accesses. We then provide an approach to automatically find such hyperplanes. Experimental evaluation on a 12-core Intel Westmere shows that diamond tiled code is able to outperform a tuned domain-specific stencil code generator by 10 to 40 percent, and previous compiler techniques by a factor of 1.3x to 10.1x.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
Publisher:	IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1314 USA
Additional Information:	Copy right for this article belongs to the IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1314 USA
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	20 May 2017 06:22
Last Modified:	20 May 2017 06:22
URI:	http://eprints.iisc.ac.in/id/eprint/56938

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