A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

Raja, Immanuel and Khatri, Vishal and Zahir, Zaira and Banerjee, Gaurab (2017) A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 25 (3). pp. 1044-1053.

PDF IEE_Tra_Ver_Lar_Sca_Int_Sya_25-3_1044_2017.pdf - Published Version Restricted to Registered users only Download (4MB) | Request a copy

Abstract

A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked loop-type architecture for quadrature error correction. The circuit corrects the phase error to within a 1.5 degrees up to 1 GHz and to within 3 degrees at 2 GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-mu m mixed-mode CMOS with an active area of 102 mu m x 95 mu m. The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	03 Apr 2017 04:18
Last Modified:	03 Apr 2017 04:18
URI:	http://eprints.iisc.ac.in/id/eprint/56424

Actions (login required)

View Item