Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

Makosiej, Adam and Gupta, Navneet and Vakul, Naga and Vladimirescu, Andrei and Cotofana, Sorin and Mahapatra, Santanu and Amara, Amara and Anghel, Costin (2016) Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications. In: MICRO & NANO LETTERS, 11 (12). pp. 828-831.

PDF Mic_Nan_Let_11-12_828_2016.pdf - Published Version Restricted to Registered users only Download (168kB) | Request a copy

Abstract

Tunnel-field-effect transistors (TFETs) operate by quantum band-to-band tunnelling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFET-based SRAM utilisation for Low STandby Power applications. An 8 T TFET SRAM cell operating at V-DD = 1 V, which, in contrast to other 6 T TFET SRAMs, is write-disturb- and half-selection-free is proposed. Simulations based on 30 nm p- and n-TFETs models relying on I-D, C-GS, C-GD vs. V-GS, and V-DS look-up tables extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120 and 200 mV, respectively, which are well above state of the art values repotted in the literature. When utilised in an 128 x 128-bit memory array the proposed cell enables read and write operation at 3.84 GHz and 806 MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for Internet of Things applications.

Item Type:	Journal Article
Publication:	MICRO & NANO LETTERS
Additional Information:	Copy right for this article belongs to the INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	20 Jan 2017 04:16
Last Modified:	20 Jan 2017 04:16
URI:	http://eprints.iisc.ac.in/id/eprint/55917

Actions (login required)

View Item