ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

3D Die Level Packaging for Hybrid Systems

Krishna, Vamsi NP and Sen, Prosenjit (2016) 3D Die Level Packaging for Hybrid Systems. In: IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), MAY 23-26, 2016, San Jose, CA, pp. 120-122.

[img] PDF
IEEE_Int_Int_Tec_Con_120_2016.pdf - Published Version
Restricted to Registered users only

Download (980kB) | Request a copy
Official URL: http://dx.doi.org/10.1109/IITC-AMC.2016.7507703

Abstract

The aim of this work is to develop and optimize processing technologies required for 3-D die level packaging of hybrid systems including MEMS and MOS components. In this paper we report the process development for stacking of ultra-thin silicon dies (as low as 10 mu m) and a basic 5 mu m thick MEMS device (Cantilever). SU-8 has been used as the patternable dielectric filler between the device layers.

Item Type: Conference Proceedings
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited: 07 Dec 2016 06:03
Last Modified: 07 Dec 2016 06:03
URI: http://eprints.iisc.ac.in/id/eprint/55565

Actions (login required)

View Item View Item