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Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic

Merchant, Farhad and Choudhary, Nimash and Nandy, SK and Narayan, Ranjani (2016) Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 415-420.

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Official URL: http://dx.doi.org/10.1109/VLSID.2016.113


In this paper we present different optimization techniques on look-up table based algorithms for double precision floating point arithmetic. Based on our analysis of different look-up table based algorithms in the literature, we re-engineer basics blocks of the algorithms ( i.e. multiplier(s) and adder(s)) to facilitate area and timing benefits to achieve higher performance. We propose different look-up table optimization techniques for the algorithms. We also analyze trade-off in employing exact rounding ( 0.5ulp) ( unit in the last place) in the double precision floating point unit. Based on performance and extensibility criteria we take algorithms proposed by Wong and Goto as a base case to validate our optimization techniques and compare the performance with other algorithms in the literature. We improve the performance ( latency x area) of Wong and Goto division algorithm by 26.94%.

Item Type: Conference Proceedings
Series.: International Conference on VLSI Design
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 07 Dec 2016 06:02
Last Modified: 07 Dec 2016 06:02
URI: http://eprints.iisc.ac.in/id/eprint/55562

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