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Hardware Solution For Real-time Face Recognition

Mahale, Gopinath and Mahale, Hamsika and Goel, Arnav and Nandy, SK and Bhattacharya, S and Narayan, Ranjani (2015) Hardware Solution For Real-time Face Recognition. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 81-86.

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Official URL: http://dx.doi.org/10.1109/VLSID.2015.19


The objective of this paper is to come up with a scalable modular hardware solution for real-time Face Recognition (FR) on large databases. Existing hardware solutions use algorithms with low recognition accuracy suitable for real-time response. In addition, database size for these solutions is limited by on-chip resources making them unsuitable for practical real-time applications. Due to high computational complexity we do not choose algorithms in literature with superior recognition accuracy. Instead, we come up with a combination of Weighted Modular Principle Component Analysis (WMPCA) and Radial Basis Function Neural Network (RBFNN) which outperforms algorithms used in existing hardware solutions on highly illumination and pose variant face databases. We propose a hardware solution for real-time FR which uses parallel streams to perform independent modular computations. A salient feature of proposed hardware solution is that we store a major part of data on off-chip memory in a novel format, so that latencies experienced accessing off-chip memory does not impact performance. This enables us to work on databases of very large sizes. To test functional correctness, the proposed architecture is synthesized and tested on Virtex-6 LX550T FPGA. This emulated system is able to perform 450 recognitions per second on images of size 128 x 128 with 450 classes.

Item Type: Conference Paper
Series.: International Conference on VLSI Design
Additional Information: Copy right for this article belongs to the IEEE COMPUTER SOC, 10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, CA 90720-1264 USA
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 07 Dec 2016 04:27
Last Modified: 07 Dec 2016 04:27
URI: http://eprints.iisc.ac.in/id/eprint/55443

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