Rahul, Arun S and Kaarthik, Sudharshan R and Gopakumar, K and Franquelo, Leopoldo G and Leon, Jose I (2016) A Predictive Capacitor Voltage Control of a Hybrid Cascaded Multilevel Inverter With a Single DC-Link and Reduced Common-Mode Voltage Operation. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 63 (8). pp. 5285-5292.
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Abstract
For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two-three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (V-dc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme.
Item Type: | Journal Article |
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Publication: | IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS |
Additional Information: | Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 03 Dec 2016 06:13 |
Last Modified: | 03 Dec 2016 06:13 |
URI: | http://eprints.iisc.ac.in/id/eprint/55256 |
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