Sanjeevan, Arun Rahul and Kaarthik, Sudharshan R and Gopakumar, K and Rajeevan, PP and Leon, Jose I and Franquelo, Leopoldo G (2016) Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source. In: IET POWER ELECTRONICS, 9 (3). pp. 519-528.
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In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.
| Item Type: | Journal Article |
|---|---|
| Publication: | IET POWER ELECTRONICS |
| Publisher: | INST ENGINEERING TECHNOLOGY-IET |
| Additional Information: | Copy right for this article belongs to the INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND |
| Keywords: | PWM invertors; switching convertors; bridge circuits; power factor; capacitor switching; reduced common mode voltage operation; hybrid multilevel inverter topology; DC voltage source; linear modulation; reduced CMV switching; three level flying capacitor inverter; half-bridge module; zero CMV; modulation index; capacitor voltage balancing algorithm; pole voltage redundancy; load power factor; transient conditions |
| Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
| Date Deposited: | 29 Apr 2016 05:17 |
| Last Modified: | 29 Apr 2016 05:17 |
| URI: | http://eprints.iisc.ac.in/id/eprint/53725 |
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