ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages

Kaarthik, Sudharshan R and Gopakumar, K and Cecati, Carlo and Nagy, Istvan (2016) Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 63 (3). pp. 1395-1403.

[img] PDF
IEEE_Tra_Ind_Ele_63-3_1395_2016.pdf - Published Version
Restricted to Registered users only

Download (1MB) | Request a copy
Official URL: http://dx.doi.org/10.1109/TIE.2015.2495283


Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to theIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords: Dodecagonal; level shifted carrier; multilevel inverters; pulsewidth modulation (PWM); space vector (SV); SV structure; timing calculations
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Division of Electrical Sciences > Electrical Engineering
Date Deposited: 02 Apr 2016 09:26
Last Modified: 02 Apr 2016 09:26
URI: http://eprints.iisc.ac.in/id/eprint/53541

Actions (login required)

View Item View Item