Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs

Govindarajan, R and Yang, H and Amaral, JN and Zhang, C and Gao, GR (2001) Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. In: 15th International Parallel and Distributed Processing Symposium. IPDPS 2001, 23-27 April, San Francisco,California, pp. 1-8.

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Abstract

We revisit the optimal code generation or evaluation order determination problem-the problem of generating an instruction sequence from a data dependence graph (DDG). In particular, we are interested in generating an instruction sequence S that is optimal in terms of the number of registers used by the sequence S. We call this MRIS (Minimum Register Instruction Sequence) problem. We developed an efficient heuristic solution for the MRIS problem based on the notion of instruction lineage. This solution facilitates the sharing of registers among instructions within a lineage and across lineages by exploiting the structure of a DDG. We implemented our solution on a production compiler and measured the reduction in the number of (spill) loads and (Spill) stores and the wall-clock execution time for the SPEC95 floating point benchmark suite. On average our method reduced the number of loads and stores by 11.5% and 15.9%, respectively, and decreased the total execution time by 2.5%.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	15 Feb 2006
Last Modified:	07 Jan 2013 05:41
URI:	http://eprints.iisc.ac.in/id/eprint/5337

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