ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

Tailor, Ketankumar H and Shrivastava, Mayank and Gossner, Harald and Baghini, Maryam Shojaei and Rao, Valipe Ramgopal (2015) Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (12). pp. 4097-4104.

[img] PDF
IEEE_Tra_Ele_Dev_62-12_4097_2015.pdf - Published Version
Restricted to Registered users only

Download (3MB) | Request a copy
Official URL: http://dx.doi.org/10.1109/TED.2015.2481899


In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

Item Type: Journal Article
Additional Information: Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords: Avalanche breakdown; drain-extended MOSFET (DeMOS); input-output (I/O); Kirk effect; parasitic bipolar triggering; safe operating area (SOA); shallow-trench isolation (STI); two-stage breakdown
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 30 Dec 2015 06:00
Last Modified: 30 Dec 2015 06:00
URI: http://eprints.iisc.ac.in/id/eprint/52934

Actions (login required)

View Item View Item