Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

Gupta, Ankur and Shrivastava, Mayank and Baghini, Maryam Shojaei and Sharma, Dinesh Kumar and Gossner, Harald and Rao, Ramgopal V (2015) Part I: High-Voltage MOS Device Design for Improved Static and RF Performance. In: IEEE TRANSACTIONS ON ELECTRON DEVICES, 62 (10). pp. 3168-3175.

PDF IEEE_Tra_on_Ele_Dev_62-10_3168_2015.pdf - Published Version Restricted to Registered users only Download (3MB) | Request a copy

Abstract

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON ELECTRON DEVICES
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	Advanced CMOS; drain-extended MOS (DeMOS); high-power RF; integrated RF power amplifier (PA); system-on-chip (SoC)
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	30 Oct 2015 07:09
Last Modified:	30 Oct 2015 07:09
URI:	http://eprints.iisc.ac.in/id/eprint/52585

Actions (login required)

View Item