Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath

Madhu, Kavitha T and Das, Saptarsi and Krishna, Madhava C and Nalesh, S and Nandy, SK and Narayan, Ranjani (2014) Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 215-224.

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Abstract

In this paper we present HyperCell as a reconfigurable datapath for Instruction Extensions (IEs). HyperCell comprises an array of compute units laid over a switch network. We present an IE synthesis methodology that enables post-silicon realization of IE datapaths on HyperCell. The synthesis methodology optimally exploits hardware resources in HyperCell to enable software pipelined execution of IEs. Exploitation of temporal reuse of data in HyperCell results in significant reduction of input/output bandwidth requirements of HyperCell.

Item Type:	Conference Proceedings
Publisher:	IEEE
Additional Information:	Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	09 Oct 2015 05:58
Last Modified:	09 Oct 2015 05:58
URI:	http://eprints.iisc.ac.in/id/eprint/52532

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