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Speculative Trace Scheduling in VLIW Processors

Agarwal, Manvi and Nandy, SK (2002) Speculative Trace Scheduling in VLIW Processors. In: 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD'2002, 16-18 September, Freiburg,Germany, pp. 408-413.


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VLIW processors are statically scheduled processors and their performance depends on the quality of schedules generated by the compiler's scheduler. We propose a new scheduling scheme where the application is first divided into decision trees and then further split into traces. Traces are speculatively scheduled on the processor based on their probability of execution. We have developed a tool "SpliTree" to generate traces automatically. By using dynamic branch prediction for scheduling traces our scheme achieves approximately $1.4x$ performance improvement over that using decision trees for Spec92 benchmarks simulated on $TriMedia^{tm}$.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 27 Jan 2006
Last Modified: 19 Sep 2010 04:23
URI: http://eprints.iisc.ac.in/id/eprint/5217

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