A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

Manikandan, RR and Amrutur, Bharadwaj (2015) A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs. In: MICROELECTRONICS JOURNAL, 46 (6). pp. 422-430.

PDF Mic_Ele_Jou_46-6_422_2015.pdf - Published Version Restricted to Registered users only Download (4MB) | Request a copy

Abstract

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Item Type:	Journal Article
Publication:	MICROELECTRONICS JOURNAL
Publisher:	ELSEVIER SCI LTD
Additional Information:	Copy right for this article belongs to the ELSEVIER SCI LTD, THE BOULEVARD, LANGFORD LANE, KIDLINGTON, OXFORD OX5 1GB, OXON, ENGLAND
Keywords:	Phase-locked loop (PLL); Charge-pump; Current mismatch; Reference spur; Deterministic jitter; Static phase offset
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	19 Jul 2015 09:20
Last Modified:	19 Jul 2015 09:20
URI:	http://eprints.iisc.ac.in/id/eprint/51821

Actions (login required)

View Item