A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

Manikandan, RR and Kumar, Abhishek and Amrutur, Bharadwaj (2015) A Digital Frequency Multiplication Technique for Energy Efficient Transmitters. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, APR 2015, pp. 781-785.

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Abstract

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Item Type:	Conference Proceedings
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	OSCILLATOR
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	28 Apr 2015 07:35
Last Modified:	28 Apr 2015 07:35
URI:	http://eprints.iisc.ac.in/id/eprint/51425

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