Hardware Accelerator for 3D Method of Moments based Parasitic Extraction

Devi, Anant and Gandhi, Maulik and Varghese, Kuruvilla and Gope, Dipanjan (2013) Hardware Accelerator for 3D Method of Moments based Parasitic Extraction. In: IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), DEC 12-15, 2013, Nara, JAPAN, pp. 100-103.

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Abstract

A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

Item Type:	Conference Proceedings
Additional Information:	Copyright for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	13 Jan 2015 05:14
Last Modified:	13 Jan 2015 05:14
URI:	http://eprints.iisc.ac.in/id/eprint/50657

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