Efficient Cache Exploration Method for a Tiled Chip Multiprocessor

Dani, Aparna Mandke and Srikant, YN and Amrutur, Bharadwaj (2012) Efficient Cache Exploration Method for a Tiled Chip Multiprocessor. In: 19th International Conference on High Performance Computing (HiPC), DEC 18-22, 2012, Pune, INDIA.

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Abstract

Past studies use deterministic models to evaluate optimal cache configuration or to explore its design space. However, with the increasing number of components present on a chip multiprocessor (CMP), deterministic approaches do not scale well. Hence, we apply probabilistic genetic algorithms (GA) to determine a near-optimal cache configuration for a sixteen tiled CMP. We propose and implement a faster trace based approach to estimate fitness of a chromosome. It shows up-to 218x simulation speedup over the cycle-accurate architectural simulation. Our methodology can be applied to solve other cache optimization problems such as design space exploration of cache and its partitioning among applications/ virtual machines.

Item Type:	Conference Proceedings
Series.:	Proceedings-International Conference on High Performance Computing
Publisher:	IEEE
Additional Information:	19th International Conference on High Performance Computing (HiPC), Pune, INDIA, DEC 18-22, 2012
Keywords:	genetic algorithms; performance evaluation; chip multiprocessors
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	27 Sep 2013 08:07
Last Modified:	27 Sep 2013 08:08
URI:	http://eprints.iisc.ac.in/id/eprint/47333

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