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Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Kulkarni, Abhijit and John, Vinod (2013) Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 60 (12). pp. 5820-5829.

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Official URL: http://dx.doi.org/10.1109/TIE.2012.2236998


Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Item Type: Journal Article
Additional Information: Copyright for this article belongs to the IEEE
Keywords: Converters; harmonic distortion; phase-locked loops (PLLs)
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Date Deposited: 16 Aug 2013 08:00
Last Modified: 16 Aug 2013 08:00
URI: http://eprints.iisc.ac.in/id/eprint/47023

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