Power-Performance Trade-off using Pipeline Delays

Surendra, G and Banerjee, Subhasis and Nandy, SK (2004) Power-Performance Trade-off using Pipeline Delays. In: the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, 2004, 27-30 January, Yokohama,Japan, pp. 384-386.

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Abstract

We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are normally delayed in the issue stage due to resource constraints even though their data dependencies are satisfied. Issuing ROD instructions earlier than normal and executing them on slow functional units to obtain power benefits reduce these delays. This scheme achieves around 6% to 8% power reduction with average performance degradation of about 2%. Alternatively, instead of reducing the delays faced by instructions in the pipeline, increasing them by deliberately stalling certain instructions at appropriate times minimizes the duration for which the processor is underutilized leading to 2.5-4% power savings with less than 0.3% performance degradation.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	�©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	21 Dec 2005
Last Modified:	19 Sep 2010 04:22
URI:	http://eprints.iisc.ac.in/id/eprint/4694

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