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Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

Sengupta, Amretashis and Mahapatra, Santanu (2013) Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors. In: Journal of Applied Physics, 113 (19). 194502_1-194502_7.

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Official URL: http://dx.doi.org/10.1063/1.4805059

Abstract

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

Item Type: Journal Article
Publication: Journal of Applied Physics
Publisher: American Institute of Physics
Additional Information: Copyright of this article belongs to American Institute of Physics.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 05 Jul 2013 05:28
Last Modified: 05 Jul 2013 05:28
URI: http://eprints.iisc.ac.in/id/eprint/46786

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