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USHA: unified software and hardware architecture for video decoding

Rao, Adarsha and Nandy, SK and Deprettere, Ed F and Nikolov, Hristo (2011) USHA: unified software and hardware architecture for video decoding. In: 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 5-6 June 2011, San Diego, CA, USA.

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Official URL: http://dx.doi.org/10.1109/SASP.2011.5941074


Video decoders used in emerging applications need to be flexible to handle a large variety of video formats and deliver scalable performance to handle wide variations in workloads. In this paper we propose a unified software and hardware architecture for video decoding to achieve scalable performance with flexibility. The light weight processor tiles and the reconfigurable hardware tiles in our architecture enable software and hardware implementations to co-exist, while a programmable interconnect enables dynamic interconnection of the tiles. Our process network oriented compilation flow achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi-processor, semi hardware and full hardware implementations of a video decoder. An application quality of service aware scheduler monitors and controls the operation of the entire system. We prove the concept through a prototype of the architecture on an off-the-shelf FPGA. The FPGA prototype shows a scaling in performance from QCIF to 1080p resolutions in four discrete steps. We also demonstrate that the reconfiguration time is short enough to allow migration from one configuration to the other without any frame loss.

Item Type: Conference Proceedings
Publisher: IEEE
Additional Information: Copyright of this article belongs to IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 24 Apr 2013 08:45
Last Modified: 24 Apr 2013 08:45
URI: http://eprints.iisc.ac.in/id/eprint/46261

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