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Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy

Dani, AM and Amrutur, Bharadwaj S and Srikant, YN (2011) Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy. In: 2011 Second Workshop on Architecture and Multi-Core Applications (WAMCA), 26-27 Oct. 2011, Vitoria, Espirito Santo.

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Official URL: http://dx.doi.org/10.1109/WAMCA.2011.14


Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright of this article belongs to IEEE. USA
Keywords: Power Efficient NUCA;Adaptive Optimization
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 27 Mar 2013 10:49
Last Modified: 27 Mar 2013 10:51
URI: http://eprints.iisc.ac.in/id/eprint/46122

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