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Device oriented statistical modeling method for process variability in 45nm analog CMOS technology

Ajayan, KR and Bhat, Navakanta (2011) Device oriented statistical modeling method for process variability in 45nm analog CMOS technology. In: 16th International Workshop on Physics of Semiconductor Devices, December 19, 2011, Kanpur, India.

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Official URL: http://dx.doi.org/10.1117/12.926853


With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Item Type: Conference Paper
Publisher: International Society for Optical Engineering
Additional Information: Copyright of this article belongs to International Society for Optical Engineering.
Keywords: Annealing;CMOS Technology;Device Simulation;Field Effect Transistors;Oxides;Semiconductors;Statistical Modeling;Statistical Models
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited: 20 Mar 2013 10:23
Last Modified: 20 Mar 2013 10:23
URI: http://eprints.iisc.ac.in/id/eprint/46095

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