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A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

Rajeevan, PP and Gopakumar, K (2012) A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications. In: IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 48 (6, SI). pp. 2037-2047.

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Official URL: http://dx.doi.org/10.1109/TIA.2012.2226197


A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Item Type: Journal Article
Additional Information: Copyright for this article belongs to IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, USA
Keywords: Common-mode voltage (CMV);induction motor drive;multilevel inverter
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 14 Feb 2013 10:54
Last Modified: 14 Feb 2013 10:54
URI: http://eprints.iisc.ac.in/id/eprint/45789

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