Derating Based Hardware Optimizations in Soft Error Tolerant Designs

Prasanth, V and Singh, Virendra and Parekhji, Rubin (2012) Derating Based Hardware Optimizations in Soft Error Tolerant Designs. In: 30th IEEE VLSI Test Symposium (VTS), APR 23-25, 2012, Hawaii, USA, pp. 282-287.

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Abstract

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Item Type:	Conference Proceedings
Series.:	IEEE VLSI Test Symposium
Publisher:	IEEE
Additional Information:	Copyright for the article belomgs to the IEEE.
Keywords:	Soft error mitigation;hardware derating;delayed capture methodology
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	08 Nov 2012 11:35
Last Modified:	08 Nov 2012 11:35
URI:	http://eprints.iisc.ac.in/id/eprint/45334

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