Harish, BP and Bhat, Navakanta (2012) Performance and variability trade-off with gate-to-source/drain overlap length. In: IETE Journal of Research, 58 (2). pp. 130-137.
|
PDF
IETE_jou_Res_58-2_130_2012.pdf - Published Version Download (1MB) | Preview |
Abstract
The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.
| Item Type: | Journal Article |
|---|---|
| Publication: | IETE Journal of Research |
| Additional Information: | Copyright for this article belongs to the IETE Journal of Research |
| Department/Centre: | Division of Electrical Sciences > Electrical Communication Engineering |
| Date Deposited: | 11 Sep 2012 09:59 |
| Last Modified: | 11 Sep 2012 09:59 |
| URI: | http://eprints.iisc.ac.in/id/eprint/45057 |
Actions (login required)
 |
View Item |
