ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Jandhyala, Srivatsava and Abraham, Aby and Anghel, Costin and Mahapatra, Santanu (2012) Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET. In: IEEE Transactions on Electron Devices, 59 (7). pp. 1974-1979.

[img] PDF
Iee_Tra_Ele_Dev_99-7_2012.pdf - Published Version
Restricted to Registered users only

Download (770kB) | Request a copy
Official URL: http://dx.doi.org/10.1109/TED.2012.2193887


Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Item Type: Journal Article
Publication: IEEE Transactions on Electron Devices
Publisher: IEEE
Additional Information: Copyright of this article belongs to the IEEE.
Keywords: Circuit simulation;compact modeling;double-gate MOSFET; terminal charge
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 23 Jul 2012 12:38
Last Modified: 23 Jul 2012 12:38
URI: http://eprints.iisc.ac.in/id/eprint/44819

Actions (login required)

View Item View Item