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Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Surendra, G and Banerjee, Subhasis and Nandy, SK (2003) Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. In: Design, Automation And Test in Europe Conference And Exhibition,Proceedings, MAR 03-07, 2003, Munich, Germany.

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Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.

Item Type: Conference Proceedings
Publisher: IEEE
Additional Information: Copyright 2003 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 16 Mar 2012 12:18
Last Modified: 16 Mar 2012 12:18
URI: http://eprints.iisc.ac.in/id/eprint/43799

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