Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory

Mannarswamy, SS and Govindarajan, Ramaswamy (2008) Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory. In: 2011 IEEE International Parallel & Distributed Processing Symposium (IPDPS), 16-20 May 2011, Anchorage, AK.

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Abstract

Software transactional memory (STM) has been proposed as a promising programming paradigm for shared memory multi-threaded programs as an alternative to conventional lock based synchronization primitives. Typical STM implementations employ a conflict detection scheme, which works with uniform access granularity, tracking shared data accesses either at word/cache line or at object level. It is well known that a single fixed access tracking granularity cannot meet the conflicting goals of reducing false conflicts without impacting concurrency adversely. A fine grained granularity while improving concurrency can have an adverse impact on performance due to lock aliasing, lock validation overheads, and additional cache pressure. On the other hand, a coarse grained granularity can impact performance due to reduced concurrency. Thus, in general, a fixed or uniform granularity access tracking (UGAT) scheme is application-unaware and rarely matches the access patterns of individual application or parts of an application, leading to sub-optimal performance for different parts of the application(s). In order to mitigate the disadvantages associated with UGAT scheme, we propose a Variable Granularity Access Tracking (VGAT) scheme in this paper. We propose a compiler based approach wherein the compiler uses inter-procedural whole program static analysis to select the access tracking granularity for different shared data structures of the application based on the application's data access pattern. We describe our prototype VGAT scheme, using TL2 as our STM implementation. Our experimental results reveal that VGAT-STM scheme can improve the application performance of STAMP benchmarks from 1.87% to up to 21.2%.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	compiler;software transactional memory
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	29 Dec 2011 08:51
Last Modified:	29 Dec 2011 08:51
URI:	http://eprints.iisc.ac.in/id/eprint/42943

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