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Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

Biswas, P and Narayan, R and Nandy, SK and Alle, Mythri and Varadarajan, K and Mondal, R and Udupa, PP (2010) Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. In: 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 5-7 July 2010, Lixouri, Kefalonia.

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Numerical Linear Algebra (NLA) kernels are at the heart of all computational problems. These kernels require hardware acceleration for increased throughput. NLA Solvers for dense and sparse matrices differ in the way the matrices are stored and operated upon although they exhibit similar computational properties. While ASIC solutions for NLA Solvers can deliver high performance, they are not scalable, and hence are not commercially viable. In this paper, we show how NLA kernels can be accelerated on REDEFINE, a scalable runtime reconfigurable hardware platform. Compared to a software implementation, Direct Solver (Modified Faddeev's algorithm) on REDEFINE shows a 29X improvement on an average and Iterative Solver (Conjugate Gradient algorithm) shows a 15-20% improvement. We further show that solution on REDEFINE is scalable over larger problem sizes without any notable degradation in performance.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Interdisciplinary Sciences > Computational and Data Sciences
Date Deposited: 27 Dec 2011 10:27
Last Modified: 11 Oct 2018 15:21
URI: http://eprints.iisc.ac.in/id/eprint/42918

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