Underlap Optimization in HFinFET in Presence of Interface Traps

Majumdar, Kausik and Konjady, Rajaram Shetty and Suryaprakash, Raj Tejas and Bhat, Navakanta (2011) Underlap Optimization in HFinFET in Presence of Interface Traps. In: IEEE Transactions on Nanotechnology, 10 (6). pp. 1249-1253.

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Abstract

In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significantON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.

Item Type:	Journal Article
Publication:	IEEE Transactions on Nanotechnology
Publisher:	IEEE
Additional Information:	Copyright 2011 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Coupled poisson-schrodinger equations;FinFET;HEMT;HFinFET; III-V transistor;interface traps
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited:	21 Dec 2011 09:36
Last Modified:	21 Dec 2011 09:36
URI:	http://eprints.iisc.ac.in/id/eprint/42618

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