ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer

Alle, Mythri and Nandy, SK and Biswas, J (2006) Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer. In: In Proceedings of Distributed Multimedia Systems 2006, August 30-September 1, Grand Canyon, USA.

[img] PDF
Speed_and_Area.pdf - Published Version
Restricted to Registered users only

Download (90kB) | Request a copy
Official URL: http://www.morphingmachines.com/node/12


H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

Item Type: Conference Paper
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 22 Nov 2011 09:31
Last Modified: 22 Nov 2011 09:31
URI: http://eprints.iisc.ac.in/id/eprint/42373

Actions (login required)

View Item View Item